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Cross Section of TSVs, source: P. Leduc, LETI, D43D, 2010 Ready for primetime in ASICs…almost Thru-silicon-vias (TSVs) have become a very hot topic in in recent months. Ever since Xilinx reported that they are using a 2.5D TSV approach for their Virtex-7 FPGAs (http://bit.ly/ayfOgy), the industry started to salivate with the prospects of this new technology. While this [...] A low cost package may end up raising your system costs. [...] The European Union (EU) has certainly led the charge in the elimination of many hazardous chemical for semiconductor devices with the RoHS legislation (Reduction of Hazardous Substances.) Most of these were not present in the first place or were more easily eliminated or substituted with environmentally safer materials. One material, lead, had proven to be a [...] So many of us in the semiconductors realm are guilty of using JEDEC thermal data incorrectly. I often get questions such as “how much power can this package handle” or “what’s the thermal efficiency of this package.” Unfortunately, in almost all situations these questions cannot be generally answered. The numbers we throw around for thermal performance come from the [...] As packages evolve into the 3D space or other formats of SiP (System-in-Package) integration, one thing is clear. The integration has to be planned first. This integration has to be considered from the system-level and die floorplan concurrently. I often see prospective clients with SiP solutions where various components were designed in isolation of the complementary [...] |
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