The Future of ASICs in 3D

3D technology is generating a lot of interest as a way to reduce NRE costs and speed time to market. It is in its nascency so people are looking for a single standard in through-silicon vias (TSVs). This is mainly for reducing infrastructure costs. Unfortunately, I do not think this will be the case. There are at least two fundamentally different applications for 3D technology that are driven by completely different incentives. The mobile space is driven mostly by the need for reduced power, height and area. The infrastructure and networking space is driven by the need for yield improvement and the ability to insert more memory than is monolithically possible — at  much lower power. Mobile devices need thin architectures and very thin packages. On the other hand, larger networking devices require thicker 3D-ICs or interposers in order to handle the flatness needed for larger die and the side-by-side architectures of the devices.

Basic 2.5D Structure

These are really exciting times: 3D and 2.5D technology could change the entire landscape and architecture of ASICs. This has already started in FPGAs and ASSPs, but ASICs face a particular challenge. ASICs do not generally have the benefit of high volume required to secure sources, influence foundries, and gain early access to 3D technology — which they need if they want to be in a leadership role in this implementation.

The exponentially rising cost of tapeouts at lower nodes has resulted in fewer tapeouts at these emerging technologies. Therefore, there are fewer experts in this field. Some companies will be able to spend a lot of money developing the technology and hence developing the expertise in the field. The rest of us will need to depend on strategic partnerships to help, to hand-hold, as we cross the threshold into this technology.

Foundries and assembly houses are keeping their 3D-IC cards close to their chest and waiting for industry leadership to come from the users of 2.5D and 3D technology. Obviously, they do not want to spend all that money to determine later they need to change course to follow the prevailing current.

eSilicon has already spent a good amount of time and effort on 3D- and 2.5D-IC technology. We believe that ASICs will need what we are referring to as a menu for “tiles,” such as memories, microprocessor subsystems, integrated passive devices, FPGA die, and other devices. In the eSilicon model, tiles are proven building blocks. A 2.5D or 3D-IC implementation could include tiles in leading-edge technologies like 28nm, with a lower NRE thanks to a 65nm based interposer. The proven tiles mean the design team doesn’t have to re-invent the wheel, saving time and reducing risk.

3D-IC Structure Example

We — along with our partners — are moving forward to provide leadership in the 3D-IC space. At the same time, we look within and beyond our customer base to make sure we know where the prevailing currents are flowing. I do not think any of us will have all the answers, but ongoing conversations with partners and customers are getting us closer to understanding where the need is. Once you know where the need is, the direction will be abundantly clear.

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